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Sheet目录3836

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2010 Microchip Technology Inc.

DS39616D-page 33

PIC18F2331/2431/4331/4431

3.6.4.1

Compensating with the EUSART

An adjustment may be required when the EUSART

begins generating framing errors or receives data with

errors while in Asynchronous mode. Framing errors

frequently indicate that the device clock frequency is

too high. To adjust for this, decrement the value in the

OSCTUNE register to reduce the clock frequency.

Conversely, errors in data may suggest that the clock

speed is too low; to compensate, increment the

OSCTUNE register to increase the clock frequency.

3.6.4.2

Compensating with the Timers

This technique compares the device clock speed to

that of a reference clock. Two timers may be used: one

timer clocked by the peripheral clock and the other by

a fixed reference source, such as the Timer1 oscillator.

Both timers are cleared, but the timer clocked by the

reference generates interrupts. When an interrupt

occurs, the internally clocked timer is read and both

timers are cleared. If the internally clocked timer value

is greater than expected, the internal oscillator block is

running too fast. To adjust for this, decrement the

OSCTUNE register.

3.6.4.3

Compensating with the CCP Module

in Capture Mode

A CCP module can use free-running Timer1 (or

Timer3), clocked by the internal oscillator block and an

external event with a known period (such as the AC

power frequency). The time of the first event is cap-

tured in the CCPRxH:CCPRxL registers and recorded

for later use. When the second event causes a capture,

the time of the first event is subtracted from the time of

the second event. Since the period of the external

event is known, the time difference between events can

be calculated.

If the measured time is much greater than the calcu-

lated time, the internal oscillator block is running too

fast. To compensate for this, decrement the OSCTUNE

calculated time, the internal oscillator block is running

too slow and the OSCTUNE register should be

incremented.

REGISTER 3-1:

OSCTUNE: OSCILLATOR TUNING REGISTER

U-0

R/W-0

—

TUN5

TUN4

TUN3

TUN2

TUN1

TUN0

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 7-6

Unimplemented:

Read as ‘0’

bit 5-0

TUN<5:0>:

Frequency Tuning bits

011111

= Maximum frequency

000001

000000

= Center frequency. Oscillator module is running at the calibrated frequency.

111111

100000

= Minimum frequency

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